The escalating requirements for high density and performance associated with ultra-large scale integration semiconductor devices necessitate design rules of 0.18 .mu.m and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features, e.g., of source, drain, and gate regions of transistors formed in or on a common semiconductor substrate, challenges the limitations of conventional junction and contact formation technology, including photolithographic, etching, and deposition techniques.
As a result of the ever increasing demand for large-scale and ultra-small dimensioned integrated semiconductor devices, self-aligned techniques have become the preferred technology for forming such devices in view of their simplicity and capability of high-density integration. As device dimensions decrease, both vertically and laterally, many problems arise, especially those caused by an increase in sheet resistance of the contact areas to the source and drain regions and junction leakage as junction layer thickness decreases. To overcome this problem, the use of highly electrically conductive refractory metal silicides has become commonplace in the manufacture of integrated semiconductor devices comprising, e.g., MOS type transistors. Another technique employed in conjunction with refractory metal silicide technology is the use of lightly doped drains ("LDDs"). An LDD consists of a lightly doped source/drain region (i.e., dopant density is on the order of about 9.times.10.sup.19 da/cm.sup.3) formed just at the edge of the gate region, while a more heavily doped drain region (i.e., dopant density is on the order of about 2.times.10.sup.20 da/cm.sup.3), to which ohmic contact is to be provided, is laterally displaced away from the gate by provision of a sidewall spacer on the gate electrode.
Salicide processing involves deposition of a metal that forms an intermetallic compound with silicon, but does not react with silicon oxides or silicon nitrides under normal processing conditions. Refractory metals commonly employed in salicide processing include titanium, nickel, and cobalt, each of which form very low resistivity phases with silicon, e.g., TiSi.sub.2, NiSi.sub.2, and CoSi.sub.2. In practice, the refractory metal is deposited in a uniform thickness over all exposed upper surface features of the silicon wafer, preferably by means of physical vapor deposition (PVD) from an ultra-pure sputtering target and an ultra-high vacuum, multi-chamber DC magnetron sputtering system. In MOS transistor formation, deposition is generally performed both after gate etch and after source/drain junction formation. After deposition, the refractory metal blankets the polysilicon gate electrode, the silicon oxide or nitride spacers, the silicon oxide isolation regions, and the exposed portions of thc source and drain regions. As a result of a rapid thermal annealing (RTA) process performed in an inert atmosphere, the refractory metal reacts with underlying silicon to forn electrically conductive silicide layer portions on the top surface of the gate electrode and on the exposed portions of the source and drain regions. Unreacted portions of the refractory metal layer, e.g., on the silicon oxide or silicon nitride sidewall spacers and the silicon oxide isolation regions, are then removed, e.g., by use of a wet etch process which is selective to the metal silicide portions. In some instances, e.g., with cobalt, a first RTA step may be performed at a relatively low temperature from about 400.degree. C. to about 550.degree. C. for from about 20 sec to about 120 sec in order to form first-phase CoSi which is then subjected to a second RTA step performed at a relatively high temperature from about 700.degree. C. to about 850.degree. C. for from about 20 sec to about 60 sec to convert the CoSi to second-phase, lower resistivity CoSi.sub.2. The second RTA step is performed after selective etch of the non-reacted cobalt. While titanium (Ti) is presently the most prevalent metal utilized in the IC industry for salicide processing, it has a drawback in that titanium silicide (TiSi.sub.2) sheet resistance rises dramatically due to narrow-line effects. As a consequence, the use of cobalt silicide (CoSi.sub.2) has increased as a result of its replacement of titanium silicide in salicide processing. Second-phase cobalt silicide (CoSi2) advantageously does not display narrow-line effects because it forms by a diffusion reaction mechanism rather than by the nucleation-and-growth mechanism observed with titanium silicide. See, for example, European Patent 0651076.
With either metal or reaction mechanism, silicon underlying the refractory metal layer is consumed by the silicide-forming reaction. Such silicon consumption becomes increasingly problematic as junction depth becomes shallower in order to increase switching speed. Large silicon consumption results in insufficient distance between the bottom of the metal silicide layer and the bottom of the source or drain junction, resulting in junction leakage. The amount of silicon consumption for silicidization depends upon the particular refractory metal silicide formed and is reflected by the "consumption ratio", defined as the ratio of silicon thickness consumed to the metal silicide thickness formed. Thus a low consumption ratio is desirable to minimize silicon consumption. Consumption ratios for titanium, cobalt, and nickel (the most commonly employed metals for forming metal silicides in the IC industry) are 0.9, 1.03, and 0.78, respectively, whereby nickel is clearly the metal of choice based upon this criterion. (See, for example, S. P. Murarka: "Silicides for VLSI Application.) However, it has other limitations which result in cobalt currently being the preferred metal, despite its relatively high consumption ratio for silicide formation.
Referring now to FIGS. 1(A)-1(C), shown therein are steps in a typical self-aligned metal silicide process (salicide process), illustratively cobalt silicide, for manufacturing MOS transistors and CMOS devices according to the conventional art. The term "semiconductor substrate", as used throughout the present disclosure and claims, denotes a silicon-containing semiconductor wafer, e.g., a monocrystalline Si wafer, or an epitaxial silicon-containing layer formed on a semiconductor substrate and comprising at least one region 1 of a first conductivity type. It will be appreciated that for P-MOS type transistors, the region 1 is n-type and for N-MOS type transistors, region 1 is p-type. It will be further appreciated that the substrate may comprise pluralities of n- and p-type regions arrayed in a desired pattern.
As illustrated in FIG. 1(A), reference numeral 1 indicates a portion of a silicon-containing semiconductor substrate of a first conductivity type (p or n), fabricated as a MOS transistor precursor 2 for use in a salicide process scheme. Precursor 2 is processed, as by conventional techniques not described here in detail in order to not unnecessarily obscure the primary significance of the following description. Precursor 2 comprises a plurality of, illustratively two, isolation regions 3 and 3' of a silicon oxide extending from the substrate surface 4 to a prescribed depth below the surface. A patterned gate oxide layer 5, typically comprising a silicon oxide layer about 25 .ANG. thick, is formed at preselected locations along the substrate surface 4. Gate electrode 6, typically of polysilicon, is formed over gate oxide layer 5, with spacers 7, 7', typically of a silicon nitride, formed on the side edges thereof. Source and drain regions 8, 9 of a second conductivity type, opposite that of the substrate 1, are formed, as by ion implantation (using gate electrode 6 and spacers 7, 7' as masks) and high temperature annealing to comprise very shallow and lightly doped first regions ("LDDs") 8' and 9' beneath the spacers 7, 7' and deeper, more heavily doped second regions 8" and 9" extending to the proximal edges of respective isolation regions 3, 3'.
Referring now to FIG. 1(B), a layer 10 of a refractory metal, typically cobalt, nickel or titanium, is formed, as by DC sputtering, to cover the exposed upper surfaces of the precursor 2. Suitable thicknesses of layer 10 are chosen according to the particular metal (due to the above-mentioned differences in silicon consumption ratios) and the junction depth of the second source and drain regions 8" and 9". Typical thicknesses of layer 10 range from about 70 .ANG. to about 200 .ANG. for junction depths from about 800 .ANG. to about 3000 .ANG.. Following refractory metal layer 10 deposition, a thermal treatment, typically rapid thermal annealing (RTA), is performed at a temperature and for a time sufficient to convert metal layer 10 to the corresponding electrically conductive metal silicide, e.g., CoSi.sub.2, NiSi.sub.2, or TiSi.sub.2. Typical RTA conditions for forming CoSi.sub.2 in a two-phase process may be as previously described. Since the refractory metal silicide forms only where metal layer 10 is in contact with underlying silicon, the unreacted portions of metal layer 10 formed over the silicon oxide isolation regions 3, 3' and silicon nitride sidewall spacers 7, 7' are selectively removed, as by a wet etch process.
Referring now to FIG. 1(C), the resulting structure after reaction and removal of unreacted metal comprises metal silicide layer portions 11 and 12, 12' respectively formed over gate electrode 6 and source and drain second, heavily doped regions 8" and 9". As is evident from the figure, the lower surfaces of the metal silicide layer portions are rough at the silicide-silicon interfaces, resulting in penetration of the underlying silicon substrate by the silicide. Such penetration of the silicon in the region below the source and drain second regions 8" and 9", illustratively shown at 13, can cause local shorting of the junction, thereby resulting in junction leakage. The effect of penetration is greatest with metals such as cobalt, which have relatively high silicon consumption ratios. Junction penetration can be avoided or at least minimized and junction integrity provided by increasing the junction depth of the source and drain second regions 8", 9" or by providing a thinner refractory metal layer, thereby reducing silicon consumption. However, neither of these alternatives is satisfactory: the former approach runs counter to the trend toward smaller device dimensions, both vertically and laterally, in order to increase switching speeds, and the latter approach results in an increase in metal silicide sheet resistance attendant its decrease in thickness.
A number of techniques for reducing leakage in ultra-shallow junctions employed in MOSFET type semiconductor devices have been proposed, such as are disclosed in U.S. Pat. Nos. 4,835,112; 5,208,472; 5,536,684; and 5,691,212. Such techniques, however, materially add to process complexity and include such steps as germanium implantation to retard dopant diffusion, provision of multiple dielectrics at the edges of the gate electrode, formation of a cobalt silicide-titanium nitride bilayer followed by removal of the titanium nitride layer and ion implantation of the remaining cobalt silicide layer, and formation of an amorphous silicon layer on a silicon MOS precursor and subsequent implantation, oxidation, annealing, etc. steps.
Thus, there exists a need for a simplified methodology for forming self-aligned silicide (i.e., salicide) contacts to ultra-thin transistor source and drain regions which provide low contact sheet resistance, ultra-thin conformal junctions, absence of or at least minimal junction leakage, and easy compatibility with conventional process flow for the manufacture of CMOS devices employing MOS transistors and other junction-containing semiconductor elements. There also exists a need for a process which allows for vertical self-alignment of salicide as well as underlying source/drain junctions, wherein salicide optimization for low sheet resistance is de-coupled from concerns with respect to the integrity of the underlying ultra-shallow junctions, whereby an additional degree of freedom of advanced CMOS device engineering is afforded.